1. Field
Exemplary embodiments of the present invention relate generally to a memory device.
2. Description of the Related Art
Memory devices may include a plurality of memory cells, each of which includes a cell transistor serving as a switch and a cell capacitor for storing an electrical charge representing data. More specifically, stored data in a memory cell may be determined as ‘high’ (logic 1) or ‘low’ (logic 0) depending on whether a terminal voltage of the cell capacitor is high or low.
In principle, while data is stored as an electrical charge in the cell capacitor of a memory cell, there is no power consumption and the stored data may be retained for a long period of time. However, an initial electrical charge stored in the cell capacitor may degrade overtime due to a leakage current occurring, for example, in a PN junction of a MOS transistor. IF there is a substantial degradation of the initial charge, then the stored data may be lost.
Furthermore, as the degree of integration of memory devices increases and the width of line patterns (or critical dimension) of the memory devices decreases, the capacitance of the cell capacitor is also reduced as compared with a bit line capacitance, so that a voltage difference for distinguishing data stored in a memory cell becomes smaller.
While a memory cell, with a capacitor having a reduced capacitance as described above, is coupled to a sense amplifier and is operating, a 1-bit failure may occur. Such 1-bit failure is also referred to hereinafter as an intermittent failure.
For a specific memory cell intermittent failures may occur only sporadically, making their detection and correction problematic. A memory device such as a DRAM typically performs a refresh operation on a constant cycle. For example, an intermittent failure may occur during the time interval of a refresh operation, rendering a typical refresh operation ineffective in correcting it. Furthermore, even though a failed cell detected through a test in a production stage of a memory device may be repaired with a redundancy cell, intermittent failure may also occur in a memory cell not detected as a failed cell during production.